The present invention relates to estimating decoupling capacitance, and more particularly to a decoupling capacitance estimation and insertion flow for ASIC designs.
In deep sub-micron ASIC design, with decreasing supply voltages and noise margin, and higher clock speeds, core noise is one of the most significant signal integrity problems facing a chip designer. Core noise, or instantaneous voltage drop, is due to a large demand for current across a chip in a short period of time. Instantaneous voltage drop has been linked to the following problems in integrated circuits; high performance clock jitter (cycle-to-cycle), clock skew balanced delay chain matching and clock balancing, tight hold time margin paths and scan shift chain, and jitter sensitive I/O interfaces, such as DDR and source synchronous. Instantaneous voltage drop (IVD) can also cause functional failures if not addressed properly in the design phase.
One of the most effective ways to reduce power supply noise is to increase on-chip decoupling capacitance (dcap) by adding decoupling capacitors to the circuit layout. Decoupling capacitors can be designed into the layout before or after the design is complete. Although adding decoupling capacitors is an effective method for combating IVD, the current method for estimating and adding decoupling capacitors to a chip design has disadvantages.
One disadvantage is that an integrated package level and chip level power bus model with switching and timing information is needed to accurately analyze such voltage variations over time. The current static analysis methodology relies on average power calculations to analyze and design the power distribution. There is a deficiency in the current voltage drop analysis flow in that it only takes into account the average voltage drop. Peak currents may occur between four and five times the average current estimated by conventional analysis, resulting in short duration peak voltage drops between four and five times on the chip over what was predicted, not including the package and board voltage drop. Therefore, the number of decoupling capacitors that will be placed on the chip may not be adequate to handle the underestimation of the peak voltage drops.
Another disadvantage is that if the number of decoupling capacitors is initially underestimated by the voltage drop simulation, and more must be added after the chip design is complete, then the chip may no longer have an adequate amount of area to place the additional decoupling capacitors.
A further deficiency with the current dynamic spice-like voltage drop simulation is that it is slow and time-consuming. Once a chip design nears completion, further testing and analysis are performed, followed by refinements to the design, including the decoupling capacitors. With each iteration, the voltage drop simulation increases the time for that cycle to complete. With some designs, use of the simulation is not feasible in the overall ASIC design flow because of the slow turn-around time of the simulation and a limited capacity to handle large designs.
Accordingly, what is needed is an improved method for estimating the decoupling capacitance required for an ASIC design. The present invention addresses such a need.
The present invention provides a method for estimating decoupling capacitance during an ASIC design flow. The method includes precharacterizing a set of power grid structures to model their respective noise behaviors, and storing the respective noise behaviors as noise factors in a table. During the design flow for a current design that includes at least. one of the precharacterized power grid structures, the corresponding noise factor from the table is used to calculate decoupling capacitance for the current design.
According to the present invention, components that are commonly used in ASIC designs are precharacterized for future use in a table look-up approach, thereby eliminating the need to perform these steps during the actual design flow, and therefore reducing the time to perform the decoupling capacitance estimation.